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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. adp3334 high accuracy, low i q , anycap adjustable low dropout regulator features high accuracy over line and load: 0.9% @ 25 c, 1.8% over temperature 500 ma current capability ultralow dropout voltage requires only c o = 1.0 f for stability anycap = stable with any type of capacitor (including mlcc) current and thermal limiting low noise low shutdown current: < 1.0 a (typ) 2.6 v to 11 v supply range 1.5 v to 10 v output range ?0 c to +85 c ambient temperature range applications cellular phones tft lcd modules camcorders, cameras networking systems, dsl/cable modems cable set-top boxes dsp supplies personal digital assistants general description the adp3334 is a member of the adp333x family of precision l ow dropout anycap voltage regulators. the adp3334 operates with an input voltage range of 2.6 v to 11 v and delivers a continuous load current up to 500 ma. the novel anycap architecture requires only a very small 1 ? output capacitor for stability, and the ldo is insensitive to the capacitor? equivalent series resistance (esr). this makes the adp3334 stable with any capacitor, including ceramic (mlcc) types for space restricted applications. the adp3334 achieves exceptional accuracy of ?.9% at room temperature and ?.8% over temperature, line, and load. the dropout voltage of the adp3334 is only 200 mv (typical) at 500 ma. this device also includes a safety current limit, ther- mal overload protection, and a shutdown feature. in shutdown mode, the ground current is reduced to less than 1 ?. the adp3334 has low quiescent current of 90 ? (typical) in light load situations. functional block diagram thermal protection cc in adp3334 out gnd q1 band gap ref driver g m fb sd the adp3334 is available in three different package options: 1. excellent thermal capability, space saving 3 mm 3 mm lfcsp. 2. popular low profile msop-8. 3. traditional thermal enhanced soic-8. c nr adp3334 out v in in gnd v out on off in out r1 r2 sd c in 1 f fb c out 1 f figure 1. typical application circuit
rev. b ? adp3334?pecifications 1, 2, 3 (v in = 6.0 v, c in = c out = 1.0 f, t a = 40 c to +85 c, unless otherwise noted.) parameter symbol conditions min typ max unit output voltage accuracy 4 v out v in = v out(nom) + 0.4 v to 11 v ?.9 +0.9 % i l = 0.1 ma to 500 ma t a = 25? v in = v out(nom) + 0.4 v to 11 v ?.8 +1.8 % i l = 0.1 ma to 500 ma t a = 85? v in = v out(nom) + 0.4 v to 11 v ?.3 +2.3 % i l = 0.1 ma to 500 ma t j = 150? line regulation 4 v in = v out(nom) + 0.4 v to 11 v 0.04 mv/v i l = 0.1 ma t a = 25? load regulation i l = 0.1 ma to 500 ma 0.04 mv/ma t a = 25? dropout voltage v drop v out = 98% of v out(nom) i l = 500 ma 200 400 mv i l = 300 ma 140 250 mv i l = 100 ma 60 140 mv i l = 1 ma 10 mv peak load current i ldpk v in = v out(nom) + 1 v 800 ma output noise v noise f = 10 hz?00 khz, c l = 10 ? 27 ? rms i l = 500 ma, c nr = 10 nf f = 10 hz?00 khz, c l = 10 ? 45 ? rms i l = 500 ma, c nr = 0 nf ground current 5 in regulation i gnd i l = 500 ma 4.5 10 ma i l = 300 ma 2.6 6 ma i l = 50 ma 0.5 1.5 ma i l = 0.1 ma 90 130 ? in dropout i gnd v in = v out(nom) ?100 mv 150 450 ? i l = 0.1 ma in shutdown i gndsd sd = 6 v, v in = 11 v 0.9 3 a shutdown threshold voltage v thsd ldo off 2.0 v ldo on 0.4 v sd input current i sd 0 sd 5 v 1.2 3 a output current in shutdown i osd sd = 2 v, v in = 11 v 0.01 5 ? notes 1 all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc) methods. 2 ambient temperature of 85? corresponds to a junction temperature of 125? under pulsed full load test conditions. 3 application stable with no load. 4 v in = 2.6 v to 11 v for v out(nom) 2.2 v. 5 ground current includes current through external resistors. specifications subject to change without notice.
rev. b adp3334 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adp3334 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratsings * input supply voltage . . . . . . . . . . . . . . . . . . . ?.3 v to +16 v shutdown input voltage . . . . . . . . . . . . . . . . ?.3 v to +16 v power dissipation . . . . . . . . . . . . . . . . . . . . internally limited operating ambient temperature range . . . . ?0? to +85? operating junction temperature range . . . ?0? to +150? storage temperature range . . . . . . . . . . . . ?5? to +150? ja 2-layer soic-8 . . . . . . . . . . . . . . . . . . . . . . . . 122.3?/w ja 4-layer soic-8 . . . . . . . . . . . . . . . . . . . . . . . . . 86.6?/w ja 2-layer lfcsp-8 . . . . . . . . . . . . . . . . . . . . . . . . . . 62?/w ja 4-layer lfcsp-8 . . . . . . . . . . . . . . . . . . . . . . . . . . 48?/w ja 2-layer msop-8 . . . . . . . . . . . . . . . . . . . . . . . . . 220?/w ja 4-layer msop-8 . . . . . . . . . . . . . . . . . . . . . . . . . 158?/w lead temperature range (soldering 6 sec) . . . . . . . . . . 300? * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only. functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configurations ordering guide package package model output description option brand adp3334ar adj standard small outline rn-8 package (soic-8) adp3334acp adj lead frame chip cp-8 lla scale package (lfcsp) 3 mm 3 mm body, 8-lead adp3334arm adj msop package rm-8 lla pin function descriptions mnemonic function gnd ground pin. sd shutdown control. pulling this pin low turns on the regulator. in regulator input. out output. bypass to ground with a 1.0 ? or larger capacitor. fb feedback input. fb should be connected to an external resistor divider that sets the output voltage. nc no connection. 8 7 6 5 1 2 3 4 out out fb nc in in sd gnd top view (not to scale) adp3334arm nc = no connect top view (not to scale) 8 7 6 5 1 2 3 4 gnd sd in in nc fb out out adp3334ar nc = no connect top view* adp3334acp * pins underside nc = no connect 1 2 3 4 in in sd gnd out out fb nc 8 7 6 5
rev. b ? adp3334?ypical performance characteristics input voltage ?v ground current ? a 140 60 0 012 24 6810 120 100 40 20 80 v out = 2.2v i l = 100 a i l = 0 tpc 3. ground current vs. supply voltage junction temperature ? c ground current ?ma 8 6 ?0 125 ?5 0 25 50 75 100 7 150 5 3 4 1 2 0 300ma 0 100ma i l = 500ma 50ma v in = 6v v out = 2.2v tpc 6. ground current vs. junction temperature time ? s 200 400 600 800 3 2 1 0 4 2 0 v in ?v v out ?v v out = 2.2v sd = gnd r l = 4.4 c out = 10 f c out = 1 f tpc 9. power-up response input voltage ?v output voltage ?v 2.202 2.201 2.194 24 12 6810 2.198 2.197 2.196 2.195 2.200 2.199 i l = 0 v out = 2.2v 500ma 150ma 300ma tpc 1. line regulation output voltage vs. supply voltage output load ?ma ground current ?ma 5.0 0 0 100 500 200 300 400 2.0 1.0 4.0 3.0 v in = 6v v out = 2.2v tpc 4. ground current vs. load current output load ?ma dropout voltage ?mv 250 200 0 0 100 500 200 300 400 150 100 50 v out = 2.2v tpc 7. dropout voltage vs. output current output load ?ma output voltage ?v 2.201 2.200 2.193 0 100 500 200 300 400 2.197 2.196 2.195 2.194 2.199 2.198 v out = 2.2v v in = 6v tpc 2. output voltage vs. load current junction temperature ? c output change ?% 0.5 ?0 125 ?5 0 25 50 75 100 0.3 0.4 150 0 0.1 0.2 ?.1 ?.2 500ma 300ma 0 500ma 0ma tpc 5. output voltage variation % vs. junction temperature time ?s 1 234 3.0 2.5 2.0 1.5 1.0 0.5 0 input/output voltage ?v v out = 2.2v sd = gnd r l = 4.4 tpc 8. power-up/power-down
rev. b adp3334 ? v out = 2.2v r l = 4.4 c l = 1 f time ? s 3.000 3.500 2.170 2.180 2.190 2.200 2.210 40 80 140 180 v in ?v v out ?v tpc 10. line transient response v out = 2.2v v in = 6v c l = 10 f time ? s 0 200 400 2.1 2.2 2.3 200 400 600 800 i out ?ma v out ?v tpc 13. load transient response frequency ?hz ripple rejection ?db 10 100 1k 10k 100k 1m 10m ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 c l = 1 f i l = 500ma c l = 1 f i l = 50 a c l = 10 f i l = 500ma c l = 10 f i l = 50 a v out = 2.2v tpc 16. power supply ripple rejection v out = 2.2v r l = 4.4 c l = 10 f time ? s 3.000 3.500 2.170 2.180 2.190 2.200 2.210 40 80 140 180 v in ?v v out ?v tpc 11. line transient response time ? s 0 1 2 0 2.2 200 400 600 800 v in = 4v 800m short full short 3 i out ?a v out ?v tpc 14. short circuit current 120 160 050 10 20 30 40 100 80 60 140 c l ? f rms noise ? v 40 20 0 v out = 2.0v c nr = 10nf i l = 0ma with noise reduction i l = 0ma without noise reduction i l = 500ma without noise reduction i l = 500ma with noise reduction tpc 17. rms noise vs. c l (10 hz to 100 khz) v in = 6v v out = 2.2v c l = 1 f time ? s 200 400 600 800 0 200 400 2.1 2.2 2.3 i out ?ma v out ?v tpc 12. load transient response time ? s 0 0 2 1 2 200 400 600 800 v sd ?v v out ?v 1 f 1 f 10 f 10 f v in = 6v v out = 2.2v r l = 4.4 tpc 15. turn off/on response frequency ?hz voltage noise spectral density ? v/ hz 100 10 100 1m 1k 10k 100k 10 1 0.1 0.01 0.001 v out = 2.2v i l = 1ma c l = 1 f c nr = 0 c l = 10 f c nr = 0 c l = 1 f c nr = 10nf c l = 10 f c nr = 10nf tpc 18. output noise density
rev. b ? adp3334 theory of operation the new anycap ldo adp3334 uses a single control loop for regulation and reference functions. the output voltage is sensed by a resistive voltage divider consisting of r1 and r2 that is varied to provide the available output voltage option. feedback is taken from this network by way of a series diode (d1) and a second resistor divider (r3 and r4) to the input of an amplifier. ptat v os noninverting wideband driver input q1 adp3334 compensation capacitor attenuation (v bandg ap /v out ) r1 d1 r2 r3 r4 output ptat current (a) c load r load fb gnd g m figure 2. functional block diagram a very high gain error amplifier is used to control this loop. the amplifier is constructed in such a way that equilibrium pro- duces a large, temperature-proportional input, ?ffset voltage that is repeatable and very well controlled. the temperature- propo rtional offset voltage is combined with the complementary diode voltage to form a ?irtual band gap?voltage, implicit in the network although it never appears explicitly in the circuit. u lti mately, this patented design makes it possible to control the loop with only one amplifier. this technique also improves the n oise characteristics of the amplifier by pro viding more flex ibil ity on the trade-off of noise sources that leads to a low noise design. the r1, r2 divider is chosen in the same ratio as the band gap v oltage to the output volt age. although the r1, r2 resistor divider is loaded by the diode d1 and a second divider consisting of r3 a nd r4, the values can be chosen to produce a temperature stable output. this unique arrangement specifically corrects for the loading of the divider, thus avoiding the error resulting from base current loading in conventional circuits. the patented amplifier controls a new and unique noninverting d river that drives the pass transistor, q1. the use of this special noninverting driver enables the frequency compensa tion to include the load capacitor in a pole-splitting arrangement to achieve reduced sensitivity to the value, type, and esr of the load capacitance. most ldos place very strict requirements on the range of esr values for the output capacitor because they are difficult to stabilize d ue to the uncertainty of load capacitance and resistance. m ore- over, the esr value, required to keep conventional ldos stable, changes depending on load and temperature. these esr limita- ti ons make designing with ldos more difficult because of their unclear specifications and extreme varia tions over temperature. with the adp3334 anycap ldo, this is no longer true. it can be used with virtually any good quality capacitor, with no con- straint on the minimum esr. this innovative design allows the circuit to be stable with just a small 1 m f capacitor on the out- put. additional advantages of the pole-splitting scheme include superior line noise rejection and very high regulator gain, which lead to excellent line and load regulation. an impressive ?.8% accuracy is guaranteed over line, load, and temperature. additional features of the circuit include current limit and ther- mal shutdown. application information output capacitor as with any micropower device, output transient response is a function of the output capacitance. the adp3334 is stable with a wide range of capacitor values, types, and esr (anycap). a capacitor as low as 1 ? is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. the adp3334 is stable with extremely low esr capacitors (esr 0), such as multilayer ceramic capacitors (mlcc) or oscon. note that the effective capacitance of some capacitor types may fall below the minimum over the operating temperature range or with the application of a dc voltage. input bypass capacitor an input bypass capacitor is not strictly required but is advisable in any application involving long input wires or high source impedance. connecting a 1 ? capacitor from in to ground r educes the circuit? sensitivity to pc board layout. if a larger value output capacitor is used, then a larger value input capaci- tor is also recommended. noise reduction capacitor a noise reduction capacitor (c nr ) can be placed between the output and the feedback pin to further reduce the noise by 6d b to 10 db (tpc 18). low leakage capacitors in the 100 pf to 1 nf range provide the best performance. since the feedback pin (fb) is internally connected to a high impedance node, any connection to this node should be carefully done to avoid noise pickup from external sources. the pad con nected to this pin should be as small as possible, and long pc board traces are not recomm ended. when adding a noise reduction capacitor, maintain a mini- mum load current of 1 ma when not in shutdown. it is important to note that as c nr increases, the turn-on time will be delayed. with c nr values of 1 nf, this delay may be on the order of several milliseconds. c nr adp3334 out v in in gnd v out on off in out r1 r2 sd c in 1 f fb c out 1 f figure 3. typical application circuit output voltage the adp3334 has an adjustable output voltage that can be set by an external resistor divider. the output voltage will be divided by r1 and r2 and then fed back to the fb pin.
rev. b adp3334 ? to have the lowest possible sensitivity of the output voltage to temperature variations, it is important that the value of the parallel resistance of r 1 and r 2 be kept as close as possible to 50 k w . rr rr k 12 12 50 + =w (1) also, for the best accuracy over temperature, the feedback volt- age should be set for 1.178 v: vv r rr fb out = + ? ? ? 2 12 (2) where v out is the desired output voltage and v fb is the virtual band gap voltage. note that v fb does not actually appear at the fb pin due to loading by the internal ptat current. combining the above equations and solving for r 1 and r 2 gives the following formulas: rk v v out fb 150 = ? ? ? w (3) r k v v fb out 2 50 1 = - ? ? ? w (4) table i. feedback resistor selection v out (v ) r1 (1% resistor) (k ) r2 (1% resistor) (k ) 1.5 63.4 232.0 1.8 76.8 147.0 2.2 93.1 107.0 2.7 115.0 88.7 3.3 140.0 78.7 5.0 210.0 64.9 10.0 422.0 56.2 using standard 1% values, as shown in table i, will sacrifice some output voltage accuracy. to estimate the overall output voltage accuracy, it is necessary to take into account all sources of error. the accuracy given in the specifications table does not take into account the error introduced by the feedback resistor divider ratio or the error introduced by the parallel combination of the feedback resistors. the error in the parallel combination of the feedback resistors causes the reference to have a wider variation over temperature. to estimate the variation , calculate the worst-case error from 50 k w , and then use the graph in figure 4 to estimate the additional change in the output voltage over the operating temperature range. for example: v in = 5 v v out = 3.3 v r1 = 140 k w , 1% r2 = 78.7 k w , 1% rp error ?% output error ?% 3.0 2.5 2.0 1.5 1.0 0.5 0 023456 figure 4. output voltage error vs. parallel resistance error the actual output voltage can be calculated using the following equation. v.v r r v.v out out =+ ? ? ? = 1 178 1 2 1 3 274 (5) so worst-case error will occur when r1 has a ?% tolerance and r2 has a +1% tolerance. recalculating the output voltage, the parallel resistance and error are: v.v . . v.v resistor divider error . . out out =+ ? ? ? = =- ? ? ? =- 1 178 138 6 79 5 1 3 232 3 232 33 1 100 2 1 %.% (6) r rr rr .. .. . k r error . parallel parallel = + = + = =- ? ? ? = 12 12 138 6 79 5 138 6 79 5 50 51 50 51 50 1 100 1 02 w %.% (7) so, from the graph in figure 4, the output voltage error is estimated to be an additional 0.25%. the error budget is 1.8% (the initial output voltage accuracy over temperature), plus 2.1% (resistor divider error), plus 0.25% (parallel resis- tance error) for a worst-case total of 4.15%. thermal overload protection the adp3334 is protected against damage from excessive power dissipation by its thermal overload protection circuit, which limits the die temperature to a maximum of 165?. under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above 165?, the output current is reduced until the die temperature has dropped to a safe level. the output current is restored when the die temperature is reduced.
rev. b ? adp3334 current and thermal limit protections are intended to protect the device against accidental overload conditions. for normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 150?. calculating junction temperature device power dissipation is calculated as follows: pvv i vi di no ut load in gnd =- () + () (8) where i load and i gnd are load current and ground current, v in and v out are input and output voltages, respectively. assuming i load = 400 ma , i gnd = 4 ma , v in = 5.0 v and v out = 2.8 v , device power dissipation is: pmamamw d =- () + () = 528 400 5 0 4 900 .. (9) as an example, the proprietary package used in the adp3334 has a thermal resistance of 86.6?/w, significantly lower than a standard soic-8 package. assuming a 4-layer board, the junction temperature rise above ambient temperature will be approximately equal to: d t=. w cw c a j 0 900 86 6 77 9 = ./ . (10) to limit the maximum junction temperature to 150?, maxi- mum allowable ambient temperature will be: tc/wc amax = - = 150 77 9 72 1 c .. (11) the maximum power dissipation versus ambient temperature for each package is shown in figure 5. ambient temperature ? c 3.5 ?0 0 20 4 06080 power dissipation ?w 2.5 1.5 1.0 0.5 0 3.0 2.0 158 c/w msop 220 c/w msop 122 c/w soic 86 c/w soic 62 c/w lfcsp 48 c/w lfcsp figure 5. power derating curve printed circuit board layout consideration all surface-mount packages rely on the traces of the pc board to conduct heat away from the package. in standard packages, the dominant component of the heat resistance path is the plastic between the die attach pad and the individual leads. in typical thermally enhanced packages, one or more of the leads are fused to the die attach pad, significantly decreasing this component. to make the improvement mean- ingful, however, a significant copper area on the pcb must be attached to these fused pins. as an example, the patented thermal coastline lead frame design of the adp3334 uniformly minimizes the value of the dominant portion of the thermal resistance. it ensures that heat is con- ducted away by all pins of the package. this yields a very low 86.6?/w thermal resistance for the soic-8 package, without any special board layout requirements, relying only on the normal traces connected to the leads. this yields a 15% improvement in heat dissipation capability as compared to a standard soic-8 package. the thermal resistance can be decreased by an addi- tional 10% by attaching a few square centimeters of copper area to the in or out pins of the adp3334 package. it is not recommended to use solder mask or silkscreen on the pcb traces adjacent to the adp3334? pins since it will increase the junction-to-ambient thermal resistance of the package. 0.50 2x vias, 0.250 35? plating 3.36 0.90 1.80 2.36 1.90 1.40 0.30 0.73 figure 6. 3 mm x 3 mm lfcsp pad pattern (dimensions shown in millimeters) lfcsp layout considerations the lfcsp package has an exposed die paddle on the bottom, which efficiently conducts heat to the pcb. in order to achieve the optimum performance from the lfcsp package, special consideration must be given to the layout of the pcb. use the following layout guidelines for the lfcsp package. 1. the pad pattern is given in figure 6. the pad dimension should be followed closely for reliable solder joints while maintaining reasonable clearances to prevent solder bridging. 2. the thermal pad of the lfcsp package provides a low ther- mal impedance path (approximately 20?/w) to the pcb. therefore the pcb must be properly designed to effectively conduct the heat away from the package. this is achieved by adding thermal vias to the pcb, which provide a thermal path to the inner or bottom layers. see figure 5 for the rec- ommended via pattern. note that the via diameter is small to prevent the solder from flowing through the via and leaving voids in the thermal pad solder joint. note that the thermal pad is attached to the die substrate, so the thermal planes that the vias attach the package to must be electrically isolated or connected to v in . do not con- nect the thermal pad to ground.
rev. b adp3334 ? 3. the solder mask opening should be about 120 microns (4.7 mils) larger than the pad size resulting in a minimum 60 micron (2.4 mils) clearance between the pad and the solder mask. 4. the paste mask opening is typically designed to match the pad size used on the peripheral pads of the lfcsp package. this should provide a reliable solder joint as long as the stencil thickness is about 0.125 mm. the paste mask for the thermal pad needs to be designed for the maximum coverage to effectively remove the heat from the package. however, due to the presence of thermal vias and the size of the thermal pad, eliminating voids may not be possible. 5. the recommended paste mask stencil thickness is 0.125 mm. a laser cut stainless steel stencil with trapezoidal walls should be used. a ?o clean?type 3 solder paste should be used for m ount- ing the lfcsp package. also, a nitrogen purge during the reflow process is recommended. 6. the package manufacturer recommends that the reflow temperature should not exceed 220? and the time above liquidus is less than 75 seconds. the preheat ramp should be 3?/second or lower. the actual temperature profile depends on the board density and must determined by the assembly house as to what works best. use the following general guidelines when designing printed circuit boards. 1. keep the output capacitor as close as possible to the out- put and ground pins. 2. keep the input capacitor as close as possible to the input and ground pins. 3. pc board traces with larger cross sectional areas will remove more heat from the adp3334. for optimum heat transfer, specify thick copper and use wide traces. 4. use additional copper layers or planes to reduce the thermal resistance. when connecting to other layers, use multiple vias if possible. shutdown mode applying a ttl high signal to the shutdown (sd) pin or the input pin will turn the output off. pulling sd down to 0.4 v or below or tying it to ground will turn the output on. in shutdown mode, quiescent current is reduced to much less than 1 ?.
rev. b ?0 adp3334 8-lead standard small outline package [soic] narrow body (rn-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.19 (0.0075) 1.27 (0.0500) 0.41 (0.0160) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.33 (0.0130) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa outline dimensions 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 0.23 0.08 0.80 0.40 8 0 85 4 1 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc compliant to jedec standards mo-187aa coplanarity 0.10 8-lead frame chip scale package [lfcsp] 3 mm 3 mm body (cp-8) dimensions shown in millimeters 1 bottom view 0.50 bsc 0.60 max pin 1 indicator 1.50 ref 0.60 0.42 0.24 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 nom seating plane pin 1 indicator 0.90 max 0.85 nom 0.30 0.23 0.18 0.05 max 0.01 nom 0.20 ref 1.89 1.74 1.59 2 1.60 1.45 1.30 3.00 bsc sq dimensions shown are in millimeters
rev. b adp3334 ?1 revision history location page 3/03?ata sheet changed from rev. a to rev. b. edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 added text to output voltage section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 added figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 edits to calculating junction temperature section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 renumbered figures 5 and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1/03?ata sheet changed from rev. 0 to rev. a. added 8-lead lfcsp and 8-lead msop packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal edits to product title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 removed pin numbers from figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 added pinouts to pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 added text to calculating junction temperature section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 added lfcsp layout considerations section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 added figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 updated 8-lead soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
c02610??/03(b) ?2

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